PAGE:
5
/19
Intel
Fig. 4.
I80-Type Parallel Interface Read Cycle Timing
2-5-3.
SYNCHRONOUS SERIAL INTERFACE TIMING
(See Fig. 5, 6, 10, and 11)
Table-7
Item
Symbol
Min.
Max.
Unit
STB Setup Time
t
STBS
100
?
ns
STB Hold Time
t
STBH
500
?
ns
Input Signal Fall Time
t
f
?
15
ns
Input Signal Rise Time
t
r
?
15
ns
STB Pulse Width High
t
WSTB
500
?
ns
SCK Pulse Width High
t
SCKH
200
?
ns
SCK Pulse Width Low
t
SCKL
200
?
ns
SI Data Setup Time
t
DSs
100
?
ns
SI Data Hold Time
t
DHs
100
?
ns
SCK Cycle Time
t
CYCSCK
500
?
ns
SCK Wait Time Between Bytes
t
WAIT
1
?
us
SO Data Delay Time
t
DDs
?
150
ns
SO Data Hold Time
t
DHRs
5
?
ns
Note: All timing is specified using 20% and 80% of
V
cc as the reference points.
DB0-DB7
t
f
t
DHRi
t
r
t
RSH
t
RSS
t
DDi
t
CYCRD
RD/
RS
t
RDL
t
RDH
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